US 12,008,265 B2
Quality-of-service information for a multi-memory system
Saira Samar Malik, Lafayette, IN (US); Sahil Soi, Bengaluru (IN); and Taeksang Song, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 19, 2022, as Appl. No. 17/648,400.
Claims priority of provisional application 63/184,404, filed on May 5, 2021.
Prior Publication US 2022/0357889 A1, Nov. 10, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a non-volatile memory;
a volatile memory configured to operate as a cache for the non-volatile memory; and
an interface controller coupled with the non-volatile memory and the volatile memory, the interface controller operable to cause the apparatus to:
receive a set of bits from a host device during a set of clock cycles and over a command bus comprising a command select pin configured for double data rate signaling;
determine whether the set of bits represents a first command or metadata for a second command based at least in part on a state of the command select pin during at least one clock cycle of the set of clock cycles; and
determine, based at least in part on the state of the command select pin indicating that the set of bits represents metadata for the second command, quality-of-service (QoS) information for the second command based at least in part on a plurality of bits included in the set of bits, the second command comprising a read command or a write command.