US 12,008,234 B2
Managing memory in an electronic system
Scott D. Schaber, North Reading, MA (US); and Howard Lin, North Reading, MA (US)
Assigned to TERADYNE, INC., North Reading, MA (US)
Filed by Teradyne, Inc., North Reading, MA (US)
Filed on Nov. 10, 2021, as Appl. No. 17/523,175.
Prior Publication US 2023/0146534 A1, May 11, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 11/263 (2006.01); G06F 12/06 (2006.01)
CPC G06F 3/0604 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G06F 11/2635 (2013.01); G06F 12/0638 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A system comprising:
first memory;
second memory having a greater storage capacity than the first memory; and
a logic circuit configured to move test data from the second memory to the first memory while (i) reading other test data from the first memory, or (ii) both reading the other test data and processing the other test data, the logic circuit being configured to process the other test data prior to output along a test channel, where the test channel leads to a device under test (DUT) to be tested;
wherein the first memory comprises a first memory module and a second memory module; and
wherein moving the test data from the second memory to the first memory comprises reading the test data from the second memory and storing the test data, in the first memory module while reading the other test data from the second memory module.