US 12,008,066 B2
Mac processing pipeline having conversion circuitry, and methods of operating same
Frederick A. Ware, Los Altos Hills, CA (US); and Cheng C. Wang, San Jose, CA (US)
Assigned to Flex Logix Technologies, Inc., Mountain View, CA (US)
Filed by Flex Logix Technologies, Inc., Mountain View, CA (US)
Filed on Aug. 1, 2022, as Appl. No. 17/816,487.
Application 17/816,487 is a division of application No. 17/031,631, filed on Sep. 24, 2020, granted, now 11,455,368.
Claims priority of provisional application 62/909,293, filed on Oct. 2, 2019.
Prior Publication US 2022/0374492 A1, Nov. 24, 2022
Int. Cl. G06F 17/14 (2006.01); G06T 1/20 (2006.01)
CPC G06F 17/14 (2013.01) [G06T 1/20 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a multiplier-accumulator execution pipeline configured to receive (i) input data and (ii) filter weights, wherein the multiplier-accumulator execution pipeline includes a plurality of multiplier-accumulator circuits configured to process the input data, using filter weights, via a plurality of multiply and accumulate operations; and
conversion circuitry, coupled to an input of the multiplier-accumulator execution pipeline, wherein the conversion circuitry includes:
inputs configured to receive a plurality of sets of input data, wherein each set of input data includes a plurality of input data, wherein each input data of each set of input data of the plurality of sets of input data includes a floating point data format,
fixed point conversion circuitry, coupled to the inputs of the conversion circuitry and configured to convert the input data of each set of input data of the plurality of sets of input data to a fixed point data format,
Winograd conversion circuitry, coupled to the fixed point conversion circuitry and configured to (i) receive the input data of each set of input data of the plurality of sets of input data having the fixed point data format and (ii) convert each set of input data of the plurality of sets of input data to a corresponding Winograd set of input data, wherein:
each input data of each set of input data of the plurality of sets of input data converted to the corresponding Winograd set of input data, via the Winograd conversion circuitry, includes the fixed point data format, and
floating point format conversion circuitry, coupled to the Winograd conversion circuitry and configured to (i) receive the input data of each Winograd set of input data of the plurality of Winograd sets, (ii) convert each input data of each Winograd set of input data of the plurality of Winograd sets of input data to a floating point data format, and (iii) output the input data, having the floating point data format, of each Winograd set of input data of the plurality of Winograd sets of input data to the multiplier-accumulator execution pipeline;
wherein:
the fixed point conversion circuitry is configured to convert each input data, having a floating point data format, of each set of input data of the plurality of sets of input data to a block scaled fraction (BSF) data format including an exponent field and a fraction field, wherein the value of the exponent field of each input data of a particular set of input data is the same for each input data associated with the particular set of input data; and
the fixed point conversion circuitry further includes determination circuitry to determine a largest exponent of the input data of each set of input data of the plurality of sets of input data.