US 12,007,938 B2
Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width
Vedvyas Shanbhogue, Austin, TX (US); Stephen J. Robinson, Austin, TX (US); Christopher D. Bryant, Austin, TX (US); and Jason W. Brandt, Austin, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 30, 2022, as Appl. No. 17/827,882.
Application 17/827,882 is a continuation of application No. 17/131,729, filed on Dec. 22, 2020, granted, now 11,347,680.
Application 17/131,729 is a continuation of application No. 15/089,525, filed on Apr. 2, 2016, granted, now 10,901,940, issued on Jan. 26, 2021.
Prior Publication US 2022/0405234 A1, Dec. 22, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 15/80 (2006.01)
CPC G06F 15/8007 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30043 (2013.01); G06F 9/30112 (2013.01)] 42 Claims
OG exemplary drawing
 
1. A processor comprising:
a plurality of caches;
decode circuitry to decode an instruction, the instruction to provide information to address a source memory location and to provide information to address a destination memory location;
execution circuitry coupled with the decode circuitry, the execution circuitry to perform operations corresponding to the instruction, including to atomically store first data, including data loaded from the source memory location, to the destination memory location; and
a status register coupled with the execution circuitry, wherein status information is to be stored in a bit of the status register, the status information indicative of whether the first data has been stored to the destination memory location.