US 12,007,936 B2
Power efficient memory value updates for arm architectures
Regis Duchesne, Mont-de-Corsier (CH); Andrei Warkentin, South Elgin, IL (US); Cyprien Laplace, Boston, MA (US); Ye Li, Newton Highlands, MA (US); Alexander Fainkichen, Southborough, MA (US); Shruthi Hiriyuru, Boston, MA (US); and Sunil Kotian, San Jose, CA (US)
Assigned to VMware LLC, Palo Alto, CA (US)
Filed by VMware LLC, Palo Alto, CA (US)
Filed on Jan. 21, 2022, as Appl. No. 17/580,866.
Prior Publication US 2023/0237010 A1, Jul. 27, 2023
Int. Cl. G06F 9/52 (2006.01); G06F 9/30 (2018.01); G06F 15/78 (2006.01)
CPC G06F 15/7842 (2013.01) [G06F 9/30087 (2013.01); G06F 9/30123 (2013.01); G06F 9/52 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory computer-readable medium comprising executable instructions, wherein the instructions, when executed by at least one processor, cause the at least one processor to at least:
execute, by an Advanced RISC Machines (ARM) processor component, a first processing action;
transmit, by the ARM processor component, at least one command to a memory agent, the at least one command comprising instructions to perform a second processing action;
execute, by the ARM processor component, a waiting function to ensure that the second processing action is completed by the memory agent prior to a third processing action, the waiting function comprising: an exclusive load implemented using an LDXR instruction at a memory location, and a wait for event implemented using a WFE instruction that causes the ARM processor component to wait in a low-power mode for an event register to be set, followed by a data barrier implemented using a DMB instruction or a DSB instruction, wherein an NSHLD option specified as instructions for the data barrier causes execution of the data barrier to provide an ordering operation that waits only for loads to complete and only out to a point of unification, thereby ensuring that the LDXR instruction and the WFE instruction are executed prior to other instructions of the waiting function, and wherein the waiting function completes the other instructions based at least in part on the event register becoming set, wherein the other instructions confirm that the event register is set by the second processing action rather than a false positive event; and
execute, by the ARM processor component, the third processing action based at least in part on completion of the waiting function.