US 12,007,929 B2
Low-latency optical connection for CXL for a server CPU
Anshuman Thakur, Beaverton, OR (US); Dheeraj Subbareddy, Portland, OR (US); MD Altaf Hossain, Portland, OR (US); Ankireddy Nalamalpu, Portland, OR (US); and Mahesh Kumashikar, Bangalore (IN)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 9, 2020, as Appl. No. 17/067,365.
Prior Publication US 2022/0114125 A1, Apr. 14, 2022
Int. Cl. G06F 13/40 (2006.01)
CPC G06F 13/4068 (2013.01) 22 Claims
OG exemplary drawing
 
1. A processor having a system on a chip (SOC) architecture, comprising:
one or more central processing units (CPUs) comprising multiple cores;
an optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path that transmits and receives an optical bit stream directly after a link layer, bypassing multiple levels of the optical CXL protocol stack; and
a CXL interface controller connected to the one or more CPUs to enable communication between the one or more CPUs and one or more CXL devices over the optical CXL communication path.