US 12,007,920 B2
Scalable interrupts
Jeffrey E. Gonion, Campbell, CA (US); Charles E. Tucker, Campbell, CA (US); Tal Kuzi, Tel Aviv (IL); Richard F. Russo, San Jose, CA (US); Mridul Agarwal, Sunnyvale, CA (US); Christopher M. Tsay, Austin, TX (US); Gideon N. Levinsky, Cedar Park, TX (US); Shih-Chieh Wen, San Jose, CA (US); and Lior Zimet, Kerem Maharal (IL)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Apr. 17, 2023, as Appl. No. 18/301,837.
Application 18/301,837 is a continuation of application No. 17/246,311, filed on Apr. 30, 2021, granted, now 11,630,789.
Claims priority of provisional application 63/077,375, filed on Sep. 11, 2020.
Prior Publication US 2023/0251985 A1, Aug. 10, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/24 (2006.01); G06F 1/26 (2006.01)
CPC G06F 13/24 (2013.01) [G06F 1/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a first integrated circuit (IC) including a first interrupt controller; and
a second IC, co-packaged with the first IC, and including:
a second plurality of cluster interrupt controllers, wherein a given cluster interrupt controller of the second plurality of cluster interrupt controllers is associated with a second plurality of processors; and
a second interrupt controller, coupled to the second plurality of cluster interrupt controllers, and configured to:
in response to an interrupt from a first interrupt source on the second IC, attempt to deliver the interrupt to the second plurality of cluster interrupt controllers; and
in response to receiving non-acknowledge (NACK) responses from the second plurality of cluster interrupt controllers, communicate the interrupt to the first interrupt controller.