US 12,007,896 B2
Apparatuses, systems, and methods for configuring combined private and shared cache levels in a processor-based system
Richard James Shannon, Portland, OR (US); Stephan Jean Jourdan, Santa Clara, CA (US); Matthew Robert Erler, Portland, OR (US); and Jared Eric Bendt, Hillsboro, OR (US)
Assigned to Ampere Computing LLC, Santa Clara, CA (US)
Filed by Ampere Computing LLC, Santa Clara, CA (US)
Filed on Jun. 7, 2022, as Appl. No. 17/834,682.
Claims priority of provisional application 63/208,730, filed on Jun. 9, 2021.
Prior Publication US 2022/0398196 A1, Dec. 15, 2022
Int. Cl. G06F 12/084 (2016.01)
CPC G06F 12/084 (2013.01) [G06F 2212/60 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A processor-based system, comprising:
a first processing core including a configurable combined private and shared cache, the configurable combined private and shared cache configured to include a shared cache portion,
the shared cache portion configured to be associated with a first client application; and
a second processing core including a configurable combined private and shared cache, the configurable combined private and shared cache of the second processing core comprising a shared cache portion configured to be associated with the first client application.