US 12,007,860 B2
Salvaging bad blocks in a memory device
Sri Rama Namala, San Jose, CA (US); Lu Tong, Singapore (SG); Kristopher Kopel, Boise, ID (US); Sheng-Huang Lee, Meridian, ID (US); and Chang H. Siau, Saratoga, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 6, 2022, as Appl. No. 18/075,958.
Application 18/075,958 is a continuation of application No. 17/396,083, filed on Aug. 6, 2021, granted, now 11,537,484.
Claims priority of provisional application 63/071,014, filed on Aug. 27, 2020.
Prior Publication US 2023/0111510 A1, Apr. 13, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/20 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01)
CPC G06F 11/2094 (2013.01) [G11C 16/0483 (2013.01); G06F 2201/85 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a processor;
a memory, storing instructions, which when executed, causes the processor to perform operations comprising:
identifying that a first deck of a block of three-dimensional NAND has a defect of a type from an identified list of defect types;
identifying that a second deck of the block does not have a defect from the identified list of defect types;
testing the second deck to determine if it meets at least one quality criterion;
responsive to determining that the second deck meets at least one quality criterion, marking the second deck as salvageable;
receiving a memory device request;
identifying a bias voltage for the first deck of the block; and
servicing the memory device request serviced using NAND cells in the second deck, the servicing the memory device request comprising disabling the first deck during the servicing by applying the bias voltage to word lines of the first deck.