CPC G06F 11/08 (2013.01) [G11C 8/06 (2013.01)] | 20 Claims |
1. A semiconductor device comprising:
an error check execution signal generation circuit configured to generate an error check execution signal for performing an error check operation when an ECS (Error Check and Scrub) command that is generated based on a refresh command is input; and
an ECS control circuit configured to:
generate an ECS active command and an ECS read command for performing the error check operation based on the ECS command and the error check execution signal, and
successively generate the ECS read commands to perform the error check operation.
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