US 12,007,826 B2
Unified retention and wake-up clamp apparatus and method
Charles Augustine, Portland, OR (US); Pascal Meinerzhagen, Hillsboro, OR (US); Suyoung Bang, Hillsboro, OR (US); Abdullah Afzal, Austin, TX (US); Karthik Subramanian, Austin, TX (US); Muhammad Khellah, Tigard, OR (US); and Arvind Raman, Austin, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 19, 2020, as Appl. No. 17/128,076.
Claims priority of provisional application 63/081,228, filed on Sep. 21, 2020.
Prior Publication US 2022/0091652 A1, Mar. 24, 2022
Int. Cl. G06F 1/32 (2019.01); G06F 1/08 (2006.01); G06F 1/10 (2006.01); G06F 1/12 (2006.01); G06F 1/324 (2019.01); G06F 1/3296 (2019.01); H03K 19/0175 (2006.01)
CPC G06F 1/324 (2013.01) [G06F 1/08 (2013.01); G06F 1/12 (2013.01); G06F 1/3296 (2013.01); H03K 19/017509 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of power gates coupled to an input power supply rail and an output power supply rail;
a shifter to generate a control word to control the plurality of power gates; and
a controller to instruct the shifter when to shift up a value of the control word, shift down the value of the control word, or maintain the value of the control word, wherein the controller is to shift up or shift in non-monotonic manner to reduce error between a reference beat frequency and a beat frequency of a free-running oscillator.