US 12,007,441 B2
3D stacked die test architecture
Lee D. Whetsel, Parker, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jun. 12, 2023, as Appl. No. 18/208,366.
Application 18/208,366 is a division of application No. 17/885,472, filed on Aug. 10, 2022, granted, now 11,675,007.
Application 17/885,472 is a division of application No. 17/323,666, filed on May 18, 2021, granted, now 11,428,736, issued on Aug. 30, 2022.
Application 17/323,666 is a division of application No. 16/718,453, filed on Dec. 18, 2019, granted, now 11,047,912, issued on Jun. 29, 2021.
Application 16/718,453 is a division of application No. 16/229,647, filed on Dec. 21, 2018, granted, now 10,564,220, issued on Feb. 18, 2020.
Application 16/229,647 is a division of application No. 15/652,911, filed on Jul. 18, 2017, granted, now 10,197,626, issued on Feb. 5, 2019.
Application 15/652,911 is a division of application No. 15/340,507, filed on Nov. 1, 2016, granted, now 9,753,085, issued on Sep. 5, 2017.
Application 15/340,507 is a division of application No. 14/978,752, filed on Dec. 22, 2015, granted, now 9,513,336, issued on Dec. 6, 2016.
Application 14/978,752 is a division of application No. 14/547,830, filed on Nov. 19, 2014, granted, now 9,261,559, issued on Feb. 16, 2016.
Application 14/547,830 is a division of application No. 13/587,522, filed on Aug. 16, 2012, granted, now 8,924,802, issued on Dec. 30, 2014.
Claims priority of provisional application 61/524,632, filed on Aug. 17, 2011.
Prior Publication US 2023/0324812 A1, Oct. 12, 2023
Int. Cl. G01R 31/3185 (2006.01); G01R 31/317 (2006.01); G01R 31/3177 (2006.01)
CPC G01R 31/318555 (2013.01) [G01R 31/31723 (2013.01); G01R 31/31724 (2013.01); G01R 31/31725 (2013.01); G01R 31/3177 (2013.01); G01R 31/318508 (2013.01); G01R 31/318513 (2013.01); G01R 31/318597 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a parallel test data input (PTDI) bus;
a parallel test data input/output (PTDIO) bus;
a first surface coupled to the PTDI bus and the PTDIO bus;
a second surface opposite the first surface, wherein the second surface is coupled to the PTDI bus and the PTDIO bus;
a first parallel test circuit coupled to the PTDI bus, wherein the first parallel test circuit includes a first parallel test data output (PTDO);
a second parallel test circuit coupled to the PTDI bus, wherein the second parallel test circuit includes a second PTDO;
a first comparator coupled to the first PTDO and the PTDIO bus, wherein the first comparator includes a first comparator output;
a second comparator coupled to the second PTDO and the PTDIO bus, wherein the second comparator includes a second comparator output;
a first gate circuit coupled to the first comparator output, wherein the first gate circuit includes an output coupled to the PTDIO bus; and
a second gate circuit coupled to the second comparator output, wherein the second gate circuit includes an output coupled to the PTDIO bus.