CPC G01R 31/318555 (2013.01) [G01R 31/31723 (2013.01); G01R 31/31724 (2013.01); G01R 31/31725 (2013.01); G01R 31/3177 (2013.01); G01R 31/318508 (2013.01); G01R 31/318513 (2013.01); G01R 31/318597 (2013.01)] | 20 Claims |
1. A device comprising:
a parallel test data input (PTDI) bus;
a parallel test data input/output (PTDIO) bus;
a first surface coupled to the PTDI bus and the PTDIO bus;
a second surface opposite the first surface, wherein the second surface is coupled to the PTDI bus and the PTDIO bus;
a first parallel test circuit coupled to the PTDI bus, wherein the first parallel test circuit includes a first parallel test data output (PTDO);
a second parallel test circuit coupled to the PTDI bus, wherein the second parallel test circuit includes a second PTDO;
a first comparator coupled to the first PTDO and the PTDIO bus, wherein the first comparator includes a first comparator output;
a second comparator coupled to the second PTDO and the PTDIO bus, wherein the second comparator includes a second comparator output;
a first gate circuit coupled to the first comparator output, wherein the first gate circuit includes an output coupled to the PTDIO bus; and
a second gate circuit coupled to the second comparator output, wherein the second gate circuit includes an output coupled to the PTDIO bus.
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