CPC G01R 31/318536 (2013.01) [G01R 31/318547 (2013.01); G01R 31/31704 (2013.01); G01R 31/3185 (2013.01); G01R 31/318558 (2013.01); G01R 31/318563 (2013.01); G01R 31/318583 (2013.01); G06F 11/267 (2013.01); G06F 30/333 (2020.01); G11C 29/32 (2013.01); G11C 2029/3202 (2013.01)] | 20 Claims |
1. A computer-implemented method for forming scan chains for a test mode among a plurality of test modes of an integrated circuit, comprising:
identifying scan chain elements in a design of the integrated circuit associated with the test mode, wherein the scan chain elements comprise integrated circuit elements that are configured to be connected together into scan chains;
grouping the scan chain elements based on scan chain element grouping criteria into a plurality of scan chain groups;
identifying a number of scan chains for the test mode;
assigning each scan chain to one of the plurality of scan chain groups;
balancing scan chain elements within each of the plurality of scan chain groups among the scan chains assigned to the each scan chain group, wherein balancing includes reducing a difference between numbers of scan chain elements in each scan chain assigned to the each scan chain group; and
connecting scan chain elements to form the number of scan chains for the test mode in response to the scan chain element balancing.
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