US 12,007,439 B1
Method and apparatus for integrated circuit testing
Kuo-Min Liao, Taichung (TW); Tien-Yu Liao, Taichung (TW); and Chien-Han Liao, Taichung (TW)
Assigned to Winbond Electronics Corp., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Jan. 3, 2023, as Appl. No. 18/149,165.
Int. Cl. G01R 31/3183 (2006.01); G01R 31/3193 (2006.01)
CPC G01R 31/318371 (2013.01) [G01R 31/31932 (2013.01); G01R 31/31935 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A testing method for an integrated circuit, suitable for an electronic apparatus having a processor, and comprising:
operating a tester to perform a qualitative testing on devices in the integrated circuit by following electrical addresses of the devices, and to introduce an original verification pattern during the qualitative testing, such that a verification pattern corresponding to the original verification pattern can be converted from a raw data of a result of the qualitative testing;
converting the raw data to a test graph presented by physical addresses, by using pre-determined scramble equations; and
identifying portions of the verification pattern appeared in the test graph and comparing the portions of the verification pattern with corresponding portions of the original verification pattern by pattern recognition, and correcting the pre-determined scramble equations according to comparison result.