US 12,007,438 B2
Method and system for testing an integrated circuit
Chi-Che Wu, Hsinchu (TW); Tsung-Yang Hung, Hsinchu County (TW); and Ming-Yih Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Feb. 9, 2023, as Appl. No. 18/166,756.
Application 18/166,756 is a continuation of application No. 17/023,226, filed on Sep. 16, 2020, granted, now 11,579,191.
Claims priority of provisional application 63/041,236, filed on Jun. 19, 2020.
Prior Publication US 2023/0194598 A1, Jun. 22, 2023
Int. Cl. G01R 31/28 (2006.01)
CPC G01R 31/2896 (2013.01) [G01R 31/2834 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
testing a plurality of scan chains in a plurality of shift cycles to obtain a plurality of values;
determining at least one fail chain in the plurality of scan chains and determining at least one fail shift cycle corresponding to at least one fail value in the plurality of values;
generating a mapping table, including the plurality of shift cycles, the plurality of values, and a plurality of pins outputting the plurality of values;
mapping, through the mapping table, the at least one fail chain and the at least one fail shift cycle to the plurality of scan chains to identify an at least one fail flip flop; and
identifying at least one fault site corresponding to the at least one fail flip flop.