US 12,007,431 B2
Test circuit and method for operating the same
Chia-Wei Huang, Hsinchu (TW); Wei-Jhih Wang, Hsinchu (TW); Cheng-Cheng Kuo, Hsinchu (TW); and Yuan-Yao Chang, Kaohsiung County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Aug. 27, 2021, as Appl. No. 17/459,989.
Prior Publication US 2023/0066905 A1, Mar. 2, 2023
Int. Cl. G01R 31/28 (2006.01); H01L 21/66 (2006.01)
CPC G01R 31/2831 (2013.01) [H01L 22/34 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A wafer, comprising:
a die;
a scribe line adjacent to the die; and
a test circuit adjacent to the scribe line, the test circuit including:
a first switch configured to turn on or turn off a first set of devices under test (DUTs) arranged in a first column;
a second switch configured to turn on or turn off a second set of DUTs arranged in a second column;
a third switch configured to simultaneously couple a first DUT of the first set of DUTs and a second DUT of the second set of DUTs to a signal supply node; and
a fourth switch configured to simultaneously couple the first DUT and the second DUT to a signal receive node, wherein the fourth switch has a node directly coupled to the first DUT, the second DUT, and the third switch, and wherein there is no switch connected between the first DUT and the second DUT.