CPC G01R 31/275 (2013.01) [G01R 1/07342 (2013.01); G01R 31/2601 (2013.01)] | 2 Claims |
1. An apparatus, comprising:
a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines;
voltage regulators positioned within the scribe lines, each voltage regulator being connected to one or more test circuits, the voltage regulators being controlled by a single voltage reference signal that regulates the intended supply voltage; and
selection circuitry positioned within the scribe lines, the selection circuitry governing access to a chip being tested, the selection circuitry utilizing solely pMOS transistors to direct current from the chip being tested to a selected source measurement unit.
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