US 12,007,429 B2
Apparatus and method for managing power of test circuits
Patrick G. Drennan, Gilbert, AZ (US); Joseph S. Spector, Austin, TX (US); and Richard Wunderlich, Austin, TX (US)
Assigned to IC ANALYTICA, LLC, Austin, TX (US)
Filed by IC ANALYTICA, LLC, Austin, TX (US)
Filed on Jun. 24, 2022, as Appl. No. 17/848,972.
Claims priority of provisional application 63/215,060, filed on Jun. 25, 2021.
Prior Publication US 2022/0413037 A1, Dec. 29, 2022
Int. Cl. G01R 31/27 (2006.01); G01R 1/073 (2006.01); G01R 31/26 (2020.01)
CPC G01R 31/275 (2013.01) [G01R 1/07342 (2013.01); G01R 31/2601 (2013.01)] 2 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines;
voltage regulators positioned within the scribe lines, each voltage regulator being connected to one or more test circuits, the voltage regulators being controlled by a single voltage reference signal that regulates the intended supply voltage; and
selection circuitry positioned within the scribe lines, the selection circuitry governing access to a chip being tested, the selection circuitry utilizing solely pMOS transistors to direct current from the chip being tested to a selected source measurement unit.