US 12,007,424 B2
Substrate and material characterisation method and device
Kamal Samanta, Basingstoke (GB)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Atsugi (JP)
Appl. No. 17/441,039
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Atsugi (JP)
PCT Filed Feb. 7, 2020, PCT No. PCT/GB2020/050284
§ 371(c)(1), (2) Date Sep. 20, 2021,
PCT Pub. No. WO2020/201679, PCT Pub. Date Oct. 8, 2020.
Claims priority of application No. 1904448 (GB), filed on Mar. 29, 2019.
Prior Publication US 2022/0214390 A1, Jul. 7, 2022
Int. Cl. G01R 27/26 (2006.01); H01P 3/12 (2006.01)
CPC G01R 27/2664 (2013.01) [H01P 3/121 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A device, comprising:
a planar substrate having conductive formations defining a substrate integrated waveguide test resonator, the test resonator comprising a three-dimensional region formed at least partly within the substrate having first and second planar conductive layers extending parallel to a plane of the substrate and one or more conductive sidewall formations perpendicular to the plane of the substrate defining a resonator side wall extending around the three-dimensional region,
wherein one planar conductive layer of the first and second planar conductive layers includes a test port comprising a conductive test connection electrically isolated from a rest of the one planar conductive layer, and
wherein the test port comprises an aperture formed in the one planar conductive layer, the conductive test connection being formed entirely within the aperture with a gap between the conductive test connection and the rest of the one planar conductive layer.