CPC B60W 30/09 (2013.01) [B60W 50/14 (2013.01); G01S 13/931 (2013.01); B60W 2420/403 (2013.01)] | 11 Claims |
1. A failure detection circuit for an image sensor, comprising:
a first input node coupled to a reference voltage;
an array of second input nodes, each second input node coupled to receive a signal from a bitline of a bitline array in an image sensor comprising an array of pixels, wherein each pixel is coupled to at least one bitline of the bitline array; and
an output stage coupled to generate an output voltage indicative of any of the second input nodes being lower than the reference voltage;
where each second input node of the array of second input nodes is coupled to a gate of an input transistor, all input transistors of the failure detection circuit having a source tied to a common source node and a drain tied to a common drain node; and where the first input node is coupled to a gate of a reference transistor having a source tied to the common source node.
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