| CPC H10D 30/795 (2025.01) [H01L 21/28123 (2013.01); H10D 30/0273 (2025.01); H10D 30/6211 (2025.01); H10D 30/6212 (2025.01); H10D 30/792 (2025.01); H10D 30/797 (2025.01); H10D 62/021 (2025.01); H10D 64/015 (2025.01); H10D 64/017 (2025.01); H01L 21/28079 (2013.01); H01L 21/28088 (2013.01); H01L 21/28194 (2013.01); H10D 30/601 (2025.01)] | 11 Claims |
|
[ 10. A semiconductor device comprising:
a semiconductor substrate having:
an element formation region that, in a perspective view of the semiconductor device, extends in a first direction and a second direction, wherein a first extension of the element formation region in the first direction is greater than a second extension of the element formation region in the second direction,
a silicon channel region of the element formation region, and
silicon germanium source-drain regions of the element formation region;
a gate electrode configured to extend, in the perspective view, along the first direction and the second direction, wherein a first extension of the gate electrode in the first direction is less than a second extension of the gate electrode in the second direction, so that:
the element formation region crosses the gate electrode,
the gate electrode is on the element formation region, and
the silicon channel region is between the silicon germanium source-drain regions and under the gate electrode;
element isolation regions that, in the perspective view, are:
buried in the semiconductor substrate, and
between the gate electrode and the semiconductor substrate; and
a gate insulating film that, in a vertical sectional view of the semiconductor device, is:
between the gate electrode and the silicon channel region, and
between the gate electrode and the element isolation regions,
wherein:
the first direction is orthogonal to the second direction,
the element formation region protrudes from a base portion of the semiconductor substrate so that the element formation region, in the vertical sectional view, is between the element isolation regions,
the silicon germanium source-drain regions are on both sides of the gate electrode and extend below upper surfaces of the element isolation regions,
depressions into the upper surfaces of the element isolation regions flank the silicon channel region,
the gate electrode extends into the depressions so that, in the vertical sectional view, an upper surface of the gate electrode is above bottom surfaces of the depressions, and
junction positions of the silicon germanium source-drain regions are deeper than surfaces of the element isolation regions.]
|