US 12,329,045 B2
Phase change memory programming current leakage reduction
Injo Ok, Loudonville, NY (US); Soon-Cheon Seo, Glenmont, NY (US); Alexander Reznicek, Troy, NY (US); Youngseok Kim, Upper Saddle River, NJ (US); and Timothy Mathew Philip, Albany, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 7, 2021, as Appl. No. 17/543,957.
Prior Publication US 2023/0180639 A1, Jun. 8, 2023
Int. Cl. H10N 70/20 (2023.01); H10N 70/00 (2023.01)
CPC H10N 70/231 (2023.02) [H10N 70/011 (2023.02); H10N 70/826 (2023.02); H10N 70/8616 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a dielectric layer;
a bottom heater within the dielectric layer;
a phase change memory stack comprising a bottom projection liner electrode upon the dielectric layer and upon the bottom heater, a phase change memory material upon the bottom projection liner electrode, a top electrode upon the phase change memory material, an encapsulation column that extends from a top surface of the top electrode to a top surface of the dielectric layer, and an airgap within the encapsulation column.