| CPC H10N 50/80 (2023.02) [H10N 50/01 (2023.02)] | 20 Claims |

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1. A method, comprising:
forming a first dielectric layer over a first area of a wafer, the first area including a vertical magnetic tunnel junction structure over an etch stop layer, the etch stop layer extending through a second area of the wafer that is laterally beside the first area;
forming a second dielectric layer over the first area of the wafer and encapsulating the first dielectric layer;
forming a third dielectric layer over the first area and the second area of the wafer and encapsulating the second dielectric layer;
in a first etch operation wherein the second dielectric layer functions as an etch stop layer, forming a first opening and a second opening, the first opening being in the third dielectric layer exposing a first portion of the second dielectric layer, wherein the first portion of the second dielectric layer is positioned over an upper electrode of the vertical magnetic tunnel junction structure, the second opening exposing a first portion of the etch stop layer in the second area;
in a second etch operation, removing the first portion of the second dielectric layer exposed from the first opening and exposing a first portion of the first dielectric layer through the first opening, the first portion of the first dielectric layer positioned over the upper electrode, together with removing the first portion of the etch stop layer exposed from the second opening;
removing the first portion of the first dielectric layer through wet cleaning; and
forming a first interconnect structure in the first opening contacting the vertical magnetic tunnel junction structure together with a second interconnect structure in the second opening extending through the etch stop layer.
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