CPC H10K 59/131 (2023.02) [H10D 89/60 (2025.01); H10K 59/1213 (2023.02)] | 18 Claims |
1. An array substrate, comprising:
a base substrate, comprising a display area and a peripheral area provided on at least one side of the display area;
a plurality of sub-pixels, provided in the display area;
a plurality of source signal lines, provided in the display area and electrically connected to the plurality of sub-pixels respectively, and the plurality of source signal lines being configured to provide data signal to the plurality of sub-pixels, wherein the plurality of source signal lines extend along a first direction and arranged sequentially along a second direction different from the first direction;
a first power bus line, provided in the peripheral area and comprising a main body portion extending along the second direction;
a plurality of sub-power lines, provided in the display area and electrically connected to the plurality of sub-pixels respectively, and the plurality of sub-power lines being configured to provide first power signal to the plurality of sub-pixels, wherein the first power bus line is connected to the plurality of sub-power lines;
an electrostatic discharge protection circuit, provided on a side of the main body portion of the first power bus line away from the display area and electrically connected to the plurality of source signal lines, and comprising a plurality of first sub-signal lines and a plurality of second sub-signal lines, wherein the plurality of first sub-signal lines and the plurality of second sub- signal lines extend along the second direction and are alternately arranged along the first direction, and the main body portion of the first power bus line is adjacent to one first sub-signal line, and electrical property of the first power bus line is the same as electrical property of the one first sub- signal line.
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