| CPC H10K 59/131 (2023.02) [H10K 50/865 (2023.02); H10K 59/126 (2023.02); H10K 71/861 (2023.02)] | 7 Claims |
|
1. A display device comprising:
a driving voltage line, a data line, an initialization voltage line, and a light blocking pattern disposed on a substrate;
a semiconductor layer of a driving transistor electrically connected to the driving voltage line;
a semiconductor layer of a switching transistor electrically connected to the data line;
a semiconductor layer of an initialization transistor electrically connected to the initialization voltage line;
a gate electrode of the driving transistor overlapping the semiconductor layer of the driving transistor;
a lower storage electrode extending from the gate electrode of the driving transistor and electrically connected to the semiconductor layer of the switching transistor;
an upper storage electrode electrically connected to the semiconductor layer of the driving transistor, the light blocking pattern, and the semiconductor layer of the initialization transistor, and overlapping the lower storage electrode;
a semiconductor layer of a first auxiliary transistor disposed in a region adjacent at least one of the semiconductor layer of the switching transistor and the semiconductor layer of the initialization transistor;
a first electrode of the first auxiliary transistor electrically connected to the semiconductor layer of the first auxiliary transistor and overlapping at least one of the data line and the initialization voltage line; and
a second electrode of the first auxiliary transistor electrically connected to the semiconductor layer of the first auxiliary transistor and overlapping at least one of the lower storage electrode and the light blocking pattern.
|