US 12,328,996 B2
Display substrate, method of forming display substrate, and display device
Yongfu Diao, Beijing (CN); Chenyu Chen, Beijing (CN); and Biao Xu, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/254,168
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Nov. 29, 2019, PCT No. PCT/CN2019/121950
§ 371(c)(1), (2) Date Dec. 18, 2020,
PCT Pub. No. WO2021/102905, PCT Pub. Date Jun. 3, 2021.
Prior Publication US 2021/0335989 A1, Oct. 28, 2021
Int. Cl. H10K 59/131 (2023.01); H10K 59/12 (2023.01); H10K 59/126 (2023.01); H10K 71/00 (2023.01)
CPC H10K 59/131 (2023.02) [H10K 59/126 (2023.02); H10K 71/00 (2023.02); H10K 59/1201 (2023.02)] 23 Claims
OG exemplary drawing
 
1. A display substrate, comprising a substrate and a plurality of sub-pixels arranged in an array on the substrate, wherein the sub-pixels comprise:
a data line pattern extending in a first direction;
an initialization signal line pattern comprising a portion extending in a second direction intersecting the first direction, wherein the initialization signal line pattern is configured to transmit an initialization signal having a fixed potential; and
a sub-pixel driving circuit comprising a driving transistor, a first transistor coupled to a gate of the driving transistor, and a first shielding member coupled to the initialization signal line pattern, wherein an orthographic projection of the first shielding member on the substrate is between an orthographic projection of the first transistor on the substrate and an orthographic projection of a target data line pattern on the substrate; the target data line pattern is arranged in a next sub-pixel adjacent to a sub-pixel in the second direction,
wherein the first shielding member is at a different layer from the initialization signal line pattern, an orthographic projection of the first shielding member on the substrate and an orthographic projection of the initialization signal line pattern on the substrate overlap at a first overlapping region, and the first shielding member is coupled to the initialization signal line pattern through a first via-hole in the first overlapping region,
wherein the first transistor comprises:
a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, the sixth conductor pattern having a conductivity superior to conductivities of the fourth semiconductor pattern and the fifth semiconductor pattern; and
a third gate pattern and a fourth gate pattern coupled to the third gate pattern,
wherein the orthographic projection of the third gate pattern on the substrate partially overlaps with the orthographic projection portion of the fourth semiconductor pattern on the substrate, the orthographic projection of the fourth gate pattern on the substrate partially overlaps with the orthographic projection portion of the fifth semiconductor pattern on the substrate,
wherein an orthographic projection of the sixth conductor pattern on the substrate does not overlap with the orthographic projection of the third gate pattern on the substrate and the orthographic projection of the fourth gate pattern on the substrate,
wherein the sub-pixel driving circuit further comprises a second shielding member provided with the fixed potential, wherein an orthographic projection of the second shielding member on the substrate at least partially overlaps with the orthographic projection of the sixth conductor pattern on the substrate, and
wherein the sub-pixel further comprises a gate line pattern, a light emission control signal line pattern, a reset signal line pattern, and a power supply signal line pattern; the gate line pattern, the light emission control signal line pattern, and the reset signal line pattern each extends in the second direction, the power supply signal line pattern comprises a portion extending in the first direction.
 
12. A display substrate comprising a substrate and a plurality of sub-pixels arranged in an array on the substrate; the sub-pixels comprise:
a data line pattern extending in a first direction;
an initialization signal line pattern comprising a portion extending in a second direction intersecting the first direction, the initialization signal line pattern is configured to transmit an initialization signal having a fixed potential;
a sub-pixel driving circuit comprising a driving transistor, a first transistor coupled to a gate of the driving transistor and a first shielding member coupled to the initialization signal line pattern, wherein the first shielding member is configured to form a coupling capacitor with a first electrode of the first transistor, an orthographic projection of the first shielding member on the substrate does not overlap with an orthographic projection of a target data line pattern on the substrate; the target data line pattern is arranged in a next sub-pixel adjacent to the sub-pixel in the second direction,
wherein the first shielding member is at a different layer from the initialization signal line pattern, an orthographic projection of the first shielding member on the substrate and an orthographic projection of the initialization signal line pattern on the substrate overlap at a first overlapping region, and the first shielding member is coupled to the initialization signal line pattern through a first via-hole in the first overlapping region,
wherein the first transistor comprises:
a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, the sixth conductor pattern having a conductivity superior to conductivities of the fourth semiconductor pattern and the fifth semiconductor pattern; and
a third gate pattern and a fourth gate pattern coupled to the third gate pattern,
wherein the orthographic projection of the third gate pattern on the substrate partially overlaps with the orthographic projection portion of the fourth semiconductor pattern on the substrate, the orthographic projection of the fourth gate pattern on the substrate partially overlaps with the orthographic projection portion of the fifth semiconductor pattern on the substrate,
wherein an orthographic projection of the sixth conductor pattern on the substrate does not overlap with the orthographic projection of the third gate pattern on the substrate and the orthographic projection of the fourth gate pattern on the substrate,
wherein the sub-pixel driving circuit further comprises a second shielding member provided with the fixed potential, wherein an orthographic projection of the second shielding member on the substrate at least partially overlaps with the orthographic projection of the sixth conductor pattern on the substrate, and
wherein the sub-pixel further comprises a gate line pattern, a light emission control signal line pattern, a reset signal line pattern, and a power supply signal line pattern; the gate line pattern, the light emission control signal line pattern, and the reset signal line pattern each extends in the second direction, the power supply signal line pattern comprises a portion extending in the first direction.
 
23. A method of forming a display substrate, comprising:
forming a plurality of sub-pixels arranged in an array on a substrate, wherein the sub-pixels comprise:
a data line pattern extending in a first direction;
an initialization signal line pattern comprising a portion extending in a second direction intersecting the first direction, wherein the initialization signal line pattern is configured to transmit an initialization signal having a fixed potential;
a sub-pixel driving circuit comprising a driving transistor, a first transistor coupled to a gate of the driving transistor, and a first shielding member coupled to the initialization signal line pattern, wherein an orthographic projection of the first shielding member on the substrate is between an orthographic projection of the first transistor on the substrate and an orthographic projection of a target data line pattern on the substrate; the target data line pattern is arranged in a next sub-pixel adjacent to a sub-pixel in the second direction,
wherein the first shielding member is at a different layer from the initialization signal line pattern, an orthographic projection of the first shielding member on the substrate and an orthographic projection of the initialization signal line pattern on the substrate overlap at a first overlapping region, and the first shielding member is coupled to the initialization signal line pattern through a first via-hole in the first overlapping region,
wherein the first transistor comprises:
a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, the sixth conductor pattern having a conductivity superior to conductivities of the fourth semiconductor pattern and the fifth semiconductor pattern; and
a third gate pattern and a fourth gate pattern coupled to the third gate pattern,
wherein the orthographic projection of the third gate pattern on the substrate partially overlaps with the orthographic projection portion of the fourth semiconductor pattern on the substrate, the orthographic projection of the fourth gate pattern on the substrate partially overlaps with the orthographic projection portion of the fifth semiconductor pattern on the substrate,
an orthographic projection of the sixth conductor pattern on the substrate does not overlap with the orthographic projection of the third gate pattern on the substrate and the orthographic projection of the fourth gate pattern on the substrate, and
wherein the sub-pixel driving circuit further comprises a second shielding member provided with the fixed potential, wherein an orthographic projection of the second shielding member on the substrate at least partially overlaps with the orthographic projection of the sixth conductor pattern on the substrate; and
wherein the sub-pixel further comprises a gate line pattern, a light emission control signal line pattern, a reset signal line pattern, and a power supply signal line pattern; the gate line pattern, the light emission control signal line pattern, and the reset signal line pattern each extends in the second direction, the power supply signal line pattern comprises a portion extending in the first direction.