US 12,328,963 B2
Semiconductor device and manufacturing method therefor
Sheng Hu, Hubei (CN); and Fan Yang, Hubei (CN)
Assigned to WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD., Wuhan (CN)
Filed by WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD., Hubei (CN)
Filed on May 31, 2022, as Appl. No. 17/829,116.
Application 17/829,116 is a continuation of application No. PCT/CN2020/126046, filed on Nov. 3, 2020.
Claims priority of application No. 201911214643.5 (CN), filed on Dec. 2, 2019.
Prior Publication US 2022/0293646 A1, Sep. 15, 2022
Int. Cl. H01L 27/146 (2006.01); H01L 21/762 (2006.01); H10F 39/00 (2025.01)
CPC H10F 39/807 (2025.01) [H01L 21/76224 (2013.01); H10F 39/011 (2025.01); H10F 39/811 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate with a pixel region and a pad region;
forming a trench fill structure in the pixel region of the substrate;
forming a plug structure in the pad region of the substrate;
forming a buffer dielectric layer over both the pixel region and the pad region of the substrate so that both the trench fill structure and the plug structure are embedded in the buffer dielectric layer;
etching the buffer dielectric layer to form a first opening and a second opening, the first opening exposing at least part of the substrate around a top side wall portion of the trench fill structure and/or at least a top portion of the trench fill structure, the second opening exposing at least a top portion of the plug structure; and
forming a metal grid layer on the buffer dielectric layer in the pixel region so that the metal grid layer fills the first opening and is electrically connected to the exposed part of the substrate and/or the exposed portion of the trench fill structure,
wherein the trench fill structure comprises a high-k dielectric layer, the high-k dielectric layer being sandwiched between a side wall of a fill material and the substrate.