US 12,328,948 B1
Circuit and method for charge device model protection
Bahar Youssefi, Pointe-Claire (CA); David Michael Burnell, Ellicott City, MD (US); Jean-Francois Delage, Montreal (CA); Stephane Leclerc, Anjou (CA); and Zheng Lai, Foshan (CN)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Jul. 8, 2022, as Appl. No. 17/860,705.
Int. Cl. H10D 89/60 (2025.01); H02H 9/04 (2006.01)
CPC H10D 89/819 (2025.01) [H02H 9/046 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A charge device model (“CDM”) protection circuit comprising:
a power supply;
a primary power clamp operatively connected to the power supply;
at least one diode from a first set of diodes connected with the primary power clamp;
a second set of diodes operatively connected with the first set of diodes; and
a secondary power clamp operatively connected with at least one diode from the second set of diodes, wherein the secondary power clamp occupies less surface area than the primary power clamp, the secondary power clamp including:
a field effect transistor (“FET”) configured to vary an amplitude of an output voltage, wherein the FET includes a pulldown n-channel metal-oxide semiconductor (“nMOS”) and a pullup p-channel metal-oxide semiconductor (“pMOS”), wherein the at least one diode from the second set of diodes is connected to the secondary power clamp at a node disposed between the pulldown nMOS and the pullup pMOS, such that the at least one diode from the second set of diodes is in position to regulate a voltage level between the pulldown nMOS and the pullup pMOS,
a trigger mechanism configured to activate the FET, wherein the trigger mechanism includes a resistor/capacitor (“RC”) network, and
a triggering inverter configured to receive an input from the RC network, wherein the input of the triggering inverter is held to ground via a capacitor of the RC network.