US 12,328,946 B2
ESD protection decoupled from diffusion
Urusa Alaan, Hillsboro, OR (US); Abhishek A. Sharma, Portland, OR (US); Charles C. Kuo, Union City, CA (US); Benjamin Orr, Portland, OR (US); Nicholas Thomson, Hillsboro, OR (US); Ayan Kar, Portland, OR (US); Arnab Sen Gupta, Hillsboro, OR (US); Kaan Oguz, Beaverton, OR (US); Brian S. Doyle, Portland, OR (US); Prashant Majhi, San Jose, CA (US); Van H. Le, Portland, OR (US); and Elijah V. Karpov, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2020, as Appl. No. 17/133,595.
Prior Publication US 2022/0199609 A1, Jun. 23, 2022
Int. Cl. H02H 9/04 (2006.01); H10D 89/60 (2025.01)
CPC H10D 89/60 (2025.01) [H02H 9/046 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor substrate, wherein a transistor device is provided on the semiconductor substrate;
a stack of routing layers over the semiconductor substrate; and
a diode in the stack of routing layers, wherein the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device; and wherein the diode comprises:
a first electrode;
a semiconductor region over the first electrode; and
a second electrode over the semiconductor region.