| CPC H10D 84/853 (2025.01) [H10D 89/10 (2025.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H10D 30/797 (2025.01); H10D 62/151 (2025.01); H10D 62/822 (2025.01); H10D 64/259 (2025.01); H10D 84/017 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |
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1. A semiconductor device comprising:
a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction;
a field insulating film covering a part of side surfaces of the first to fourth active patterns;
a gate electrode provided on the first to fourth active patterns and extending in the second direction;
a gate dielectric film extending along a top surface of the field insulating film and profiles of the first to fourth active patterns exposed by the field insulating film;
a first cut region that extends from a top surface of the gate electrode to the field insulating film between the first active pattern and the second active pattern to cut the gate electrode and the gate dielectric film, and is contact with the gate electrode and the gate dielectric film; and
a second cut region that extends from the top surface of the gate electrode to the field insulating film between the third active pattern and the fourth active pattern to cut the gate electrode and the gate dielectric film, and is contact with the gate electrode and the gate dielectric film,
wherein a first width of the first cut region in the second direction at the top surface of the gate electrode is different from a second width of the second cut region in the second direction at the top surface of the gate electrode, and
wherein a first length of the first cut region from a bottom surface of the first cut region to the top surface of the gate electrode is different from a second length of the second cut region from a bottom surface of the second cut region to the top surface of the gate electrode.
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