US 12,328,938 B2
Gate structures for stacked semiconductor devices
Mrunal Abhijith Khaderbad, Hsinchu (TW); Sathaiya Mahaveer Dhanyakumar, Hsinchu (TW); Huicheng Chang, Tainan (TW); and Keng-Chu Lin, Ping-Tung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 25, 2023, as Appl. No. 18/358,312.
Application 18/358,312 is a continuation of application No. 17/461,329, filed on Aug. 30, 2021, granted, now 11,776,960.
Prior Publication US 2023/0369335 A1, Nov. 16, 2023
Int. Cl. H10D 84/85 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/853 (2025.01) [H10D 84/0193 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first transistor comprising a first semiconductor channel and a first gate structure on the first semiconductor channel;
a second transistor on the first transistor and comprising:
a second semiconductor channel; and
a second gate structure on the second semiconductor channel; and
an isolation structure isolating the first and second gate structures and in contact with the first and second semiconductor channels.