US 12,328,930 B2
Gate structures for semiconductor devices
Chung-Liang Cheng, Changhua County (TW); and Ziwei Fang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 28, 2023, as Appl. No. 18/227,744.
Application 18/227,744 is a continuation of application No. 17/397,186, filed on Aug. 9, 2021, granted, now 11,901,242.
Application 17/397,186 is a continuation of application No. 16/739,676, filed on Jan. 10, 2020, granted, now 11,088,034, issued on Aug. 10, 2021.
Claims priority of provisional application 62/851,211, filed on May 22, 2019.
Prior Publication US 2023/0377993 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 21/3213 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 64/66 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/038 (2025.01) [H01L 21/28088 (2013.01); H01L 21/28556 (2013.01); H01L 21/32133 (2013.01); H01L 21/32139 (2013.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 62/292 (2025.01); H10D 64/667 (2025.01); H10D 84/0167 (2025.01); H10D 84/0177 (2025.01); H10D 84/0193 (2025.01); H10D 84/853 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a nanostructured layer on a substrate;
forming a source/drain (S/D) region on a first portion of the nanostructured layer;
depositing a gate dielectric layer surrounding a second portion of the nanostructured layer;
depositing a first metal layer on the gate dielectric layer;
depositing a silicon-based layer on the first metal layer; and
depositing a second metal layer on the silicon-based layer.