US 12,328,927 B2
Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures
Gilbert Dewey, Beaverton, OR (US); Nazila Haratipour, Hillsboro, OR (US); Siddharth Chouksey, Portland, OR (US); Arnab Sen Gupta, Hillsboro, OR (US); Christopher J. Jezewski, Portland, OR (US); I-Cheng Tung, Hillsboro, OR (US); Matthew V. Metz, Portland, OR (US); and Anand S. Murthy, Portland, OR (US)
Assigned to Intel Coporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 25, 2020, as Appl. No. 17/033,499.
Prior Publication US 2022/0102522 A1, Mar. 31, 2022
Int. Cl. H01L 29/45 (2006.01); H01L 21/285 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 64/62 (2025.01)
CPC H10D 64/62 (2025.01) [H01L 21/28518 (2013.01); H10D 30/024 (2025.01); H10D 30/031 (2025.01); H10D 30/6211 (2025.01); H10D 30/6713 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a semiconductor structure above a substrate;
a gate electrode over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure;
a first semiconductor source or drain structure at a first end of the channel region at a first side of the gate electrode;
a second semiconductor source or drain structure at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end; and
a source or drain contact on the first or second semiconductor source or drain structure, the source or drain contact comprising an alloyed metal barrier layer and an inner conductive structure, wherein the alloyed metal barrier layer has an uppermost surface below an uppermost surface of the inner conductive structure, and wherein the alloyed metal barrier layer has a thickness along a bottom of the inner conductive structure greater than a thickness along sides of the inner conductive structure.