US 12,328,926 B1
Structures for a field-effect transistor that include a spacer structure
Dominik Martin Kleimaier, Dresden (DE); Ruchil Kumar Jain, Dresden (DE); Jan Höntschel, Dresden (DE); Peter Javorka, Dresden (DE); Steven Langdon, Dresden (DE); and Felix Holzmüller, Dresden (DE)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on May 28, 2024, as Appl. No. 18/675,367.
Int. Cl. H10D 64/27 (2025.01); H01L 21/762 (2006.01); H10D 30/60 (2025.01); H10D 86/00 (2025.01)
CPC H10D 64/514 (2025.01) [H01L 21/76267 (2013.01); H10D 30/603 (2025.01); H10D 86/201 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A structure for a field-effect transistor, the structure comprising:
a silicon-on-insulator substrate including a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a semiconductor layer on the dielectric layer, the dielectric layer having a side surface, and the semiconductor substrate having a portion adjacent to the side surface of the dielectric layer;
a gate electrode on a first portion of the semiconductor layer, the gate electrode comprising a single-crystal semiconductor material;
a source region in the semiconductor substrate;
a drain region in the semiconductor substrate;
a channel region in the semiconductor substrate, the channel region laterally between the source region and the drain region; and
a spacer structure including a first portion that directly contacts the side surface of the dielectric layer and a second portion that directly contacts the portion of the semiconductor substrate, the spacer structure including a first spacer, a second spacer, and a layer laterally between the first spacer and the second spacer, the first spacer and the second spacer comprising a first dielectric material, and the layer comprising a semiconductor material.