| CPC H10D 64/01 (2025.01) [H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 64/017 (2025.01); H10D 64/667 (2025.01); H10D 84/0177 (2025.01); H10D 84/0186 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01)] | 20 Claims |

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1. A method for forming a gate electrode, the method comprising:
forming a recess between a first gate spacer and a second gate spacer;
depositing a gate dielectric layer in the recess;
performing an atomic layer deposition process to deposit a p-type work function tuning layer over the gate dielectric layer, wherein the p-type work function tuning layer comprises carbon and nitrogen, wherein the performing the atomic layer deposition process comprises:
depositing one or more first nitride monolayers;
depositing one or more carbide monolayers over and in physical contact with the one or more first nitride monolayers; and
depositing one or more second nitride monolayers over and in physical contact with the one or more carbide monolayers, wherein the one or more first nitride monolayers, the one or more carbide monolayers, and the one or more second nitride monolayers are all deposited in situ with each other;
depositing an adhesion layer of the p-type work function tuning layer; and
depositing a conductive fill material over the adhesion layer.
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