US 12,328,922 B2
Semiconductor device and method for fabricating the same
Chih-Kai Hsu, Tainan (TW); Ssu-I Fu, Kaohsiung (TW); Yu-Hsiang Hung, Tainan (TW); Wei-Chi Cheng, Kaohsiung (TW); and Jyh-Shyang Jenq, Pingtung County (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Feb. 27, 2024, as Appl. No. 18/587,981.
Application 17/509,061 is a division of application No. 16/703,780, filed on Dec. 4, 2019, granted, now 11,189,695, issued on Nov. 30, 2021.
Application 15/983,077 is a division of application No. 15/259,060, filed on Sep. 8, 2016, granted, now 10,008,569, issued on Jun. 26, 2018.
Application 18/587,981 is a continuation of application No. 17/509,061, filed on Oct. 24, 2021, granted, now 11,948,975.
Application 16/703,780 is a continuation of application No. 15/983,077, filed on May 17, 2018, granted, now 10,541,304, issued on Jan. 21, 2020.
Claims priority of application No. 105125383 (TW), filed on Aug. 10, 2016.
Prior Publication US 2024/0194738 A1, Jun. 13, 2024
Int. Cl. H01L 29/08 (2006.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 62/00 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 62/151 (2025.01) [H10D 30/024 (2025.01); H10D 30/60 (2025.01); H10D 30/601 (2025.01); H10D 30/62 (2025.01); H10D 30/797 (2025.01); H10D 62/021 (2025.01); H10D 64/017 (2025.01); H10D 64/512 (2025.01); H10D 64/516 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01); H10D 30/0212 (2025.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a gate structure on a substrate;
a spacer around the gate structure;
a contact etch stop layer (CESL) directly contacting the spacer;
a buffer layer adjacent to the gate structure, wherein the buffer layer comprises a crescent moon shape and the buffer layer comprises an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, wherein the planar surface directly contacts the outer curve on an outer sidewall of the spacer;
a cap layer between and directly contacting the CESL and the buffer layer; and
a contact plug connecting the cap layer.