US 12,328,920 B2
Nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy
William Hsu, Portland, OR (US); Biswajeet Guha, Hillsboro, OR (US); Chung-Hsun Lin, Portland, OR (US); Anand S. Murthy, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 24, 2021, as Appl. No. 17/357,664.
Prior Publication US 2022/0416027 A1, Dec. 29, 2022
Int. Cl. H10D 62/13 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01)
CPC H10D 62/151 (2025.01) [H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01)] 9 Claims
OG exemplary drawing
 
1. An an NMOS transistor, comprising:
a plurality of horizontal nanowires above a sub-fin;
a gate stack over the plurality of horizontal nanowires and the sub-fin;
epitaxial source or drain structures on opposite ends of the plurality of horizontal nanowires; and
a doped nucleation layer at a base of the epitaxial source or drain structures adjacent to the sub-fin, the doped nucleation layer comprising a carbon-doped nucleation layer having a carbon doping concentration of 1E19/cm3 to 1E20/cm3, wherein the carbon-doped nucleation layer comprises carbon-doped silicon and phosphorous having a phosphorous concentration of 1E20/cm3 and a carbon doping of less than 1%.