| CPC H10D 62/121 (2025.01) [H01L 21/28088 (2013.01); H01L 21/30604 (2013.01); H10D 30/797 (2025.01); H10D 62/115 (2025.01); H10D 64/017 (2025.01); H10D 64/667 (2025.01)] | 20 Claims |
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1. A method, comprising:
providing a plurality of first semiconductor channels vertically spaced from one another and a plurality of second semiconductor channels vertically spaced from one another, wherein the plurality of first semiconductor channels each have a first sidewall in contact with a first dielectric structure and the plurality of second semiconductor channels each have a first sidewall in contact with a second dielectric structure, and wherein a second sidewall of each of the plurality of first semiconductor channels and a second sidewall of each of the plurality of second semiconductor channels are exposed by a cavity interposed between the first and second dielectric structures;
forming a first gate structure around at least a top surface, a bottom surface, and the second sidewall of each of the plurality of first semiconductor channels; and
forming a second gate structure around at least a top surface, a bottom surface, and the second sidewall of each of the plurality of second semiconductor channels.
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14. A method, comprising:
forming a stack over a substrate, wherein the stack comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on top of one another;
patterning the stack to remove its end portions, wherein the patterned stack comprises a plurality of first semiconductor channels and a plurality of second semiconductor channels alternately stacked on top of one another;
forming a first dielectric structure and a second dielectric structures extending along opposite sidewalls of the patterned stack;
forming a cavity extending through the patterned stack, wherein the cavity is laterally disposed opposite a first portion of the patterned stack from the first dielectric structure, and opposite a second portion of the patterned stack from the second dielectric structure;
removing, through the cavity, the second semiconductor channels of the first portion and the second semiconductor channels of the second portion;
forming a first gate structure around at least a top surface, a bottom surface, and a first sidewall of each of the plurality of first semiconductor layers of the first portion; and
forming a second gate structure around at least a top surface, a bottom surface, and a first sidewall of each of the plurality of first semiconductor layers of the second portion.
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18. A structure, comprising:
a first dielectric structure vertically extending from a substrate;
one or more first semiconductor channels extending away from the first dielectric structure along a first lateral direction, with a first sidewall of each of the one or more first semiconductor channels in contact with the first dielectric structure;
a second dielectric structure vertically extending from the substrate;
one or more second semiconductor channels extending away from the second dielectric structure along a second, opposite lateral direction, with a first sidewall of each of the one or more second semiconductor channels in contact with the second dielectric structure;
a first gate structure disposed around a top surface, a bottom surface, and a second sidewall of each of the one or more first semiconductor channels;
a second gate structure disposed around a top surface, a bottom surface, and a second sidewall of each of the one or more second semiconductor channels;
a pair of first source/drain structures disposed on opposite sides of the first gate structure along a third lateral direction perpendicular to the first and second lateral direction; and
a pair of second source/drain structures disposed on opposite sides of the second gate structure along the third lateral direction.
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