US 12,328,916 B2
CPP-agnostic source-drain contact formation for gate-all-around devices with dielectric isolation
Julien Frougier, Albany, NY (US); Ruilong Xie, Niskayuna, NY (US); Kangguo Cheng, Schenectady, NY (US); Chanro Park, Clifton Park, NY (US); and Oleg Gluschenkov, Tannersville, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Jun. 27, 2022, as Appl. No. 17/850,475.
Prior Publication US 2023/0420500 A1, Dec. 28, 2023
Int. Cl. H10D 62/10 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 62/116 (2025.01) [H10D 30/43 (2025.01); H10D 30/6713 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 84/013 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation (BDI) region;
at least one first semiconductor layer disposed within the S/D epitaxial growth in a S/D region, the at least one first semiconductor layer being an inactive channel;
at least one second semiconductor layer disposed partially within a gate region, the at least one second semiconductor layer being an active channel, and wherein the at least one second semiconductor layer extends from the gate region into a spacer region to enable a connection to the S/D epitaxial growth;
a first region with adjacent devices exhibiting a first Contacted gate Poly Pitch (CPP) defining a first gate-to-gate space, and
a second region with adjacent devices exhibiting a second CPP defining a second gate-to-gate space, where adjacent devices exhibiting the first CPP have a smaller gate-to-gate canyon than the adjacent devices exhibiting the second CPP such that the second gate-to-gate space is greater than the first gate-to-gate space.