| CPC H10D 30/6757 (2025.01) [H01L 21/0259 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01)] | 20 Claims |
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1. A semiconductor device, comprising:
an active pattern on a substrate and extending in a first direction parallel to an upper surface of the substrate;
a pair of source/drain patterns on the active pattern and spaced apart from each other in the first direction;
a gate electrode that is between the pair of source/drain patterns, crosses the active pattern, and extends in a second direction parallel to the upper surface of the substrate that is different from the first direction; and
a plurality of channel patterns stacked on the active pattern between the pair of source/drain patterns and configured to electrically connect the pair of source/drain patterns to each other,
wherein each of the channel patterns is spaced apart from another one of the channel patterns in a third direction perpendicular to the upper surface of the substrate,
wherein each of the channel patterns comprises: a first portion between the gate electrode and at least one of the pair of source/drain patterns in a plan view; and a plurality of second portions in contact with the first portion and overlapped with the gate electrode in the third direction,
wherein each of the second portions is spaced apart from another one of the second portions in the second direction,
wherein a top surface of the active pattern comprises a first recessed portion that is between the pair of source/drain patterns in the first direction, in a plan view, and
wherein the first recessed portion is between two of the second portions in the second direction, in a plan view.
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