| CPC H10D 30/6755 (2025.01) [H10D 30/6757 (2025.01); H10D 99/00 (2025.01)] | 16 Claims |
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1. A semiconductor device, comprising:
a substrate;
a second gate, located on the substrate;
a second gate dielectric layer, located on the second gate;
a semiconductor structure, located on the substrate and comprising:
a first metal oxide layer, located on the second gate dielectric layer; and
a second metal oxide layer, wherein the second metal oxide layer covers a top surface and a sidewall of the first metal oxide layer, the second metal oxide layer has a stepped structure at the sidewall of the first metal oxide layer, a carrier mobility of the first metal oxide layer is greater than a carrier mobility of a channel region of the second metal oxide layer, and a thickness of the second metal oxide layer is greater than or equal to a thickness of the first metal oxide layer;
a first gate dielectric layer, located on the semiconductor structure;
a first gate, located on the first gate dielectric layer and overlapping with the first metal oxide layer, wherein a difference between a width of the first gate and a width of the first metal oxide layer is less than 0.5 μm;
a transfer electrode, located on the second gate;
an interlayer dielectric layer, located on the transfer electrode and the first gate; and
a source and a drain, electrically connected to the second metal oxide layer, wherein the source and the drain are located on the interlayer dielectric layer, wherein the source is electrically connected to the second gate through the transfer electrode.
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