US 12,328,905 B2
Cavity spacer for nanowire transistors
William Hsu, Hillsboro, OR (US); Biswajeet Guha, Hillsboro, OR (US); Leonard Guler, Hillsboro, OR (US); Souvik Chakrabarty, Hillsboro, OR (US); Jun Sung Kang, Portland, OR (US); Bruce Beattie, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 11, 2024, as Appl. No. 18/410,681.
Application 18/410,681 is a continuation of application No. 17/725,471, filed on Apr. 20, 2022, granted, now 11,929,396.
Application 17/725,471 is a continuation of application No. 16/023,511, filed on Jun. 29, 2018, granted, now 11,342,411, issued on May 24, 2022.
Prior Publication US 2024/0347595 A1, Oct. 17, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/67 (2025.01); H10D 30/62 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 30/6735 (2025.01) [H10D 30/62 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a base comprising a semiconductor subfin;
a body over the semiconductor subfin of the base, the body comprising a semiconductor material, the body being in a form of a nanowire, nanoribbon or nanosheet and having a first end portion and a second end portion;
a gate structure wrapped around the body between the first end portion and the second end portion, the gate structure comprising a gate electrode and a gate dielectric between the gate electrode and the body;
a source region laterally adjacent to and in contact with the first end portion;
a drain region laterally adjacent to and in contact with the second end portion;
a first spacer material on opposite sides of the gate structure, the first spacer material above the first end portion of the body;
a second spacer material on opposite sides of the gate structure and under the first end portion and the second end portion of the body, the second spacer material having a bottommost surface; and
a dielectric material layer beneath the source region and beneath the drain region and in contact with a bottommost surface of the source region and the drain region, the dielectric material layer having an uppermost surface below and spaced apart from the bottommost surface of the second spacer material, and the dielectric material laterally adjacent to the semiconductor subfin.