US 12,328,904 B2
Semiconductor structure and forming method thereof
Jisong Jin, Shanghai (CN); and Abraham Yoo, Shanghai (CN)
Assigned to Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai (CN); and Semiconductor Manufacturing International (Beijing) Corporation, Beijing (CN)
Filed by Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai (CN); and Semiconductor Manufacturing International (Beijing) Corporation, Beijing (CN)
Filed on Apr. 4, 2022, as Appl. No. 17/712,498.
Claims priority of application No. 202110373963.6 (CN), filed on Apr. 7, 2021.
Prior Publication US 2022/0328642 A1, Oct. 13, 2022
Int. Cl. H01L 21/84 (2006.01); H01L 21/762 (2006.01); H01L 27/12 (2006.01); H01L 29/423 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 30/6735 (2025.01) [H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 84/017 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate comprising a discrete device unit region, wherein the device unit region comprises a plurality of sub-device regions arranged in a longitudinal direction;
protruding portions protruding from the substrate in the sub-device regions of the plurality of sub-device regions and extending in a transverse direction;
channel structure layers located on the protruding portions and spaced apart from the protruding portions, wherein each of the channel structure layers comprises one or more channel layers spaced apart from each other in sequence from a bottom to a top;
a dielectric wall located on the substrate between adjacent sub-device regions in the longitudinal direction, wherein the dielectric wall comprises a main dielectric wall portion protruding from the substrate and dielectric wall protrusions protruding from the main dielectric wall portion in the longitudinal direction, wherein the dielectric wall protrusions are in contact with side walls of the channel layers, thicknesses of end portions of the channel layers are less than thicknesses of middle portions of the channel layers;
gate structures located on the sub-device regions, the gate structures spanning tops of the channel structure layers in the sub-device regions of the plurality of sub-device regions, and surrounding the channel layers exposed from the dielectric wall; and
source/drain doped layers located on the protruding portions on two sides of the gate structures and in contact with the channel structure layers.