| CPC H10D 30/668 (2025.01) [H10D 30/0297 (2025.01); H10D 64/117 (2025.01)] | 11 Claims |
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1. A semiconductor device, comprising:
a semiconductor substrate having a first conductivity type;
a body region having a second conductivity type and formed on an upper surface layer of the substrate;
a well region having the first conductivity type and formed on a surface layer of the body region;
a split-gate structure provided within a trench passing through the well region and the body region and extending to the substrate, wherein the trench comprises a first trench region located at one end of the trench and a second trench region located at the other end of the trench, a depth of the trench in the second trench region is less than a depth of the trench in the first trench region, the split-gate structure comprising:
a first polysilicon body formed at a bottom of the first trench region and a bottom of the second trench region, and a first oxide layer being formed between the first polysilicon body, and a bottom wall and a side wall of the trench;
an isolation structure formed above the first polysilicon body; and
a second polysilicon body formed on a top side wall of the first trench region and a top of the second trench region, and a second oxide layer being formed between the second polysilicon body and the side wall of the trench, the first polysilicon body and the second polysilicon body are isolated by the isolation structure;
an interlayer dielectric layer formed on a surface of the well region and a surface of the split-gate structure, the interlayer dielectric layer further passing through the second polysilicon body in the first trench region and extending to the isolation structure, such that in the first trench region, the second polysilicon body is located between the interlayer dielectric layer and the second oxide layer; and in the second trench region, the second polysilicon body fully fills the trench above the isolation structure except the second oxide layer;
a source passing through the interlayer dielectric layer and the well region and extending to the body region;
a conductive plug, one end of the conductive plug passing through the interlayer dielectric layer and the isolation structure in the first trench region and extending into the first polysilicon body in the first trench region, the other end of the conductive plug being connected to the source, the second polysilicon body in the first trench region and the conductive plug being isolated from each other by the interlayer dielectric layer;
a gate connected to the second polysilicon body in the second trench region; and
a drain formed on a lower surface of the substrate.
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