| CPC H10D 30/6217 (2025.01) [H01L 21/32133 (2013.01); H01L 21/32136 (2013.01); H01L 21/32137 (2013.01); H10D 30/024 (2025.01); H10D 64/017 (2025.01); H10D 64/518 (2025.01); H10D 64/661 (2025.01); H10D 64/666 (2025.01); H10D 64/667 (2025.01); H10D 30/797 (2025.01)] | 20 Claims |
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1. A device comprising:
a fin structure disposed over a substrate, the fin structure extending along a first direction;
a gate stack formed over a portion of the fin structure, the gate stack extending along a second direction perpendicular to the first direction, the gate stack including a gate dielectric layer and a gate electrode layer over the gate dielectric layer, wherein a first part of the gate dielectric layer is in contact with a sidewall of the fin structure, wherein a second part of the gate dielectric layer is in contact with a top surface of an adjacent isolation feature and is substantially perpendicular to the first part of the gate dielectric layer, wherein a first part of the gate electrode layer contacts the first part of the gate dielectric layer, the first part of the gate electrode layer disposed between a second part of the gate electrode layer and the first part of the gate dielectric layer, wherein the second part of the gate dielectric layer and the first part of the gate electrode layer have first coextensive surfaces from a first edge to a second edge of the gate electrode layer defining a first width, wherein the second part of the gate dielectric layer and the second part of the gate electrode layer have second coextensive surfaces from a third edge to a fourth edge of the gate electrode layer defining a second width, wherein, as measured along a first plane parallel to a top surface of the substrate, the second width is greater than the first width, the second part of the gate electrode layer has a substantially constant width, and the first part of the gate electrode layer has a width that narrows along a direction from the second part of the gate electrode layer towards the first part of the gate dielectric layer to define a recess extending from the second part of the gate electrode layer to the first part of the gate dielectric layer, the recess parallel to the sidewall of the fin structure; and
a source/drain feature disposed on the fin structure, wherein the recess is disposed between the second part of the gate electrode layer and the source/drain feature.
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8. A device comprising:
a fin structure disposed over a semiconductor substrate;
an isolation feature adjacent to and in contact with the fin structure, wherein the fin structure protrudes above a top surface of the isolation feature to expose a first sidewall of the fin structure;
a gate stack disposed over the fin structure and the isolation feature, the gate stack including:
a gate dielectric including a first part disposed over the first sidewall of the fin structure and a second part disposed over the top surface of the isolation feature, wherein the first part of the gate dielectric is substantially perpendicular to the second part of the gate dielectric; and
a gate electrode disposed over the gate dielectric, wherein the gate electrode has a first portion laterally adjacent to the first sidewall of the fin structure, the first portion of the gate electrode in contact with the first part of the gate dielectric and with a first region of the second part of the gate dielectric along a first interface extending from a first edge to a second edge of the gate electrode, wherein the first portion of the gate electrode interposes a second portion of the gate electrode and the first part of the gate dielectric disposed over the first sidewall of the fin structure, the second portion of the gate electrode in contact with a second region of the second part of the gate dielectric along a second interface extending from a third edge to a fourth edge of the gate electrode, the second region of the second part of the gate dielectric adjacent to the first region of the second part of the gate dielectric, wherein the second interface is wider than the first interface, wherein the second interface has a substantially constant width, and wherein the first portion of the gate electrode has a second sidewall that intersects with the first part of the gate dielectric disposed over the first sidewall of the fin structure such that an acute angle is formed between the first part of the gate dielectric and the second sidewall of the first portion of the gate electrode.
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15. A device comprising:
a fin structure disposed over a semiconductor substrate, the fin structure having a sidewall surface and a top surface; and
a gate stack including a first part disposed over the top surface of the fin structure and a second part disposed over the sidewall surface of the fin structure, wherein the second part of the gate stack includes:
a gate dielectric disposed on a top surface of an isolation feature adjacent to and in contact with the fin structure; and
a gate electrode disposed on the gate dielectric, wherein the gate electrode has a first portion laterally adjacent to the sidewall surface of the fin structure, the first portion of the gate electrode in contact with a first region of the gate dielectric along a first interface extending from a first edge to a second edge of the gate electrode, wherein the first portion of the gate electrode interposes a second portion of the gate electrode and the sidewall surface of the fin structure, the second portion of the gate electrode in contact with a second region of the gate dielectric along a second interface extending from a third edge to a fourth edge of the gate electrode, the second interface adjacent to the first interface, wherein the first portion of the gate electrode becomes narrower along a direction towards the fin structure, wherein the first portion of the gate electrode is positioned closer to the fin structure than the second portion of the gate electrode, and wherein the second interface is wider than the first interface, the second interface having a substantially constant width.
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