| CPC H10D 30/615 (2025.01) [H10D 30/023 (2025.01); H10D 62/235 (2025.01); H10D 64/513 (2025.01)] | 27 Claims |
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1. An integrated circuit, comprising:
a semiconductor substrate; and
a first semiconductor component including:
a buried semiconductor region disposed in the semiconductor substrate and having a first type of conductivity;
a first gate region and a second gate region disposed at a distance from each other and each extending respectively in depth into the semiconductor substrate from a front face of the semiconductor substrate to the buried semiconductor region;
a third gate region extending in depth into the semiconductor substrate from the front face and electrically connected to the buried semiconductor region; and
an active area of the semiconductor substrate delimited by the first gate region, the second gate region and the buried semiconductor region, the active area having a second type of conductivity opposite to the first type of conductivity;
an input contact to the active area and an output contact to the active area located between the first gate region and the second gate region and at a distance from each other, the active area including:
a channel between said input contact and said output contact; and
depleted areas around the channel.
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