US 12,328,894 B2
Nitride semiconductor device
Daisuke Shibata, Kyoto (JP); Satoshi Tamura, Osaka (JP); and Masahiro Ogawa, Osaka (JP)
Assigned to PANASONIC HOLDINGS CORPORATION, Osaka (JP)
Filed by Panasonic Holdings Corporation, Osaka (JP)
Filed on Apr. 17, 2024, as Appl. No. 18/638,337.
Application 18/638,337 is a continuation of application No. 17/414,253, granted, now 11,990,542, previously published as PCT/JP2019/046003, filed on Nov. 25, 2019.
Claims priority of application No. 2018-245063 (JP), filed on Dec. 27, 2018.
Prior Publication US 2024/0266431 A1, Aug. 8, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/47 (2025.01); H10D 30/66 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01)
CPC H10D 30/477 (2025.01) [H10D 30/478 (2025.01); H10D 30/66 (2025.01); H10D 62/824 (2025.01); H10D 62/8503 (2025.01)] 6 Claims
OG exemplary drawing
 
1. A nitride semiconductor device, comprising:
a substrate;
a first nitride semiconductor layer above the substrate, the first nitride semiconductor layer being of an n-type;
a second nitride semiconductor layer above the first nitride semiconductor layer, the second nitride semiconductor layer being of a p-type;
a gate electrode covering a first opening which penetrates through the second nitride semiconductor layer to the first nitride semiconductor layer; and
a drain electrode on a side of the substrate opposite from a side of the substrate on which the first nitride semiconductor layer is located,
wherein the gate electrode includes
a third nitride semiconductor layer and a metal layer including a metal material, in the stated order from a side on which the substrate is located, and
wherein a bottom face of the third nitride semiconductor layer is closer to the drain electrode than a bottom face of the second nitride semiconductor layer is.