| CPC H10D 30/051 (2025.01) [H01L 21/02532 (2013.01); H01L 21/02642 (2013.01); H10D 30/0281 (2025.01); H10D 30/657 (2025.01); H10D 30/80 (2025.01); H10D 62/111 (2025.01); H10D 62/115 (2025.01); H10D 62/126 (2025.01); H10D 62/149 (2025.01); H10D 62/154 (2025.01); H10D 62/158 (2025.01); H10D 87/00 (2025.01)] | 14 Claims |

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1. A method of producing power semiconductor devices from a silicon-on-insulator (SOI) wafer that includes a silicon device layer, a bulk silicon wafer, and a buried oxide layer separating the silicon device layer from the bulk silicon wafer, the method comprising:
forming a hard mask on the silicon device layer, wherein the hard mask covers one or more first regions of the silicon device layer and exposes one or more second regions of the silicon device layer; and
before forming any field oxide structures and before implanting any device regions, selectively growing epitaxial silicon on the one or more second regions of the silicon device layer exposed by the hard mask such that the thickness of the one or more second regions is increased relative to the one or more first regions.
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