US 12,328,889 B2
High electron mobility transistor and method for fabricating the same
Chun-Ming Chang, Kaohsiung (TW); Che-Hung Huang, Hsinchu (TW); Wen-Jung Liao, Hsinchu (TW); Chun-Liang Hou, Hsinchu County (TW); and Chih-Tung Yeh, Taoyuan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Jun. 3, 2024, as Appl. No. 18/731,392.
Application 17/551,149 is a division of application No. 16/666,430, filed on Oct. 29, 2019, granted, now 11,239,338, issued on Feb. 1, 2022.
Application 18/731,392 is a continuation of application No. 18/215,787, filed on Jun. 28, 2023, granted, now 12,027,604.
Application 18/215,787 is a continuation of application No. 17/551,149, filed on Dec. 14, 2021, granted, now 11,735,644, issued on Aug. 22, 2023.
Claims priority of application No. 108135419 (TW), filed on Oct. 1, 2019.
Prior Publication US 2024/0322008 A1, Sep. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/01 (2025.01); H01L 21/308 (2006.01); H10D 30/47 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01)
CPC H10D 30/015 (2025.01) [H01L 21/3081 (2013.01); H10D 30/4755 (2025.01); H10D 62/824 (2025.01); H10D 62/8503 (2025.01)] 9 Claims
OG exemplary drawing
 
1. A method for fabricating a high electron mobility transistor (HEMT), comprising:
forming a buffer layer on a substrate;
forming a first barrier layer on the buffer layer;
forming a second barrier layer on the first barrier layer;
forming a first hard mask on the second barrier layer;
forming a second hard mask on the first hard mask, wherein the first hard mask and the second hard mask comprise different materials;
patterning the second hard mask, the first hard mask, the second barrier layer, the first barrier layer, and the buffer layer;
forming a third hard mask on a top surface and sidewalls of the patterned second hard mask;
removing the patterned first hard mask and the patterned second barrier layer to form a recess;
forming a p-type semiconductor layer in the recess; and
forming a source electrode and a drain electrode adjacent to two sides of the p-type semiconductor layer.