| CPC H10D 1/043 (2025.01) [H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/5223 (2013.01); H10D 1/716 (2025.01)] | 5 Claims |
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1. A semiconductor device comprising:
a silicon substrate including a logic cell region and a connection region;
an active pattern provided at the connection region and protruding from a top surface of the connection region;
a device isolation layer covering a sidewall of a lower portion of the active pattern and exposing an upper portion of the active pattern;
a metal electrode overlapping the active pattern;
a dielectric pattern between the metal electrode and the active pattern;
an epitaxial pattern adjacent to a side of the metal electrode;
a middle connection layer on the metal electrode and the epitaxial pattern, the middle connection layer comprising:
a ground contact electrically connected to the epitaxial pattern; and
an electrode contact electrically connected to the metal electrode;
an interconnection layer on the middle connection layer, the interconnection layer comprising:
a plurality of interconnection lines; and
a plurality of vias electrically connecting the plurality of interconnection lines to the middle connection layer; and
a through-via provided under the interconnection layer and penetrating the connection region,
wherein the plurality of vias comprise a first via, a second via, and a third via,
wherein the first via is connected to the through-via,
wherein the second via is connected to the ground contact,
wherein the third via is connected to the electrode contact, and
wherein the first via and the third via are electrically connected with each other through a first interconnection line of the plurality of interconnection lines.
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