US 12,328,878 B1
Integration of 2T-NC for memory and logic applications
Noriyuki Sato, Hillsboro, OR (US); Tanay Gosavi, Portland, OR (US); Rafael Rios, Austin, TX (US); Amrita Mathuriya, Portland, OR (US); Niloy Mukherjee, San Ramon, CA (US); Mauricio Manfrini, Heverlee (BE); Rajeev Kumar Dokania, Beaverton, OR (US); Somilkumar J. Rathi, San Jose, CA (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Mar. 18, 2022, as Appl. No. 17/655,432.
Application 17/655,432 is a continuation of application No. 17/654,917, filed on Mar. 15, 2022.
Int. Cl. H10B 53/30 (2023.01)
CPC H10B 53/30 (2023.02) 20 Claims
OG exemplary drawing
 
1. A system comprising:
a processor comprising a plurality of transistors in a first level, wherein individual ones of the plurality of transistors comprise:
a source;
a drain;
a gate between the source and the drain;
a drain contact coupled with the drain; and
a gate contact coupled with the gate;
a bridge structure connected between the gate contact of a first transistor in the plurality of transistors to the drain contact of a second transistor in the plurality of transistors;
a bit-cell above the first transistor and the second transistor, the bit-cell comprising:
a conductive interconnect within a first dielectric in a second level, wherein the conductive interconnect is electrically coupled with the bridge structure; and
a third level above the second level, the third level comprising:
an electrode structure on the conductive interconnect, the electrode structure comprising:
a first conductive hydrogen barrier layer; and
a first conductive fill material on the first conductive hydrogen barrier layer, wherein the electrode structure comprises a first lateral thickness;
a plurality of memory devices above the electrode structure, wherein individual ones of the plurality of memory devices comprise:
a bottom electrode;
a top electrode; and
a nonlinear polar dielectric between the top electrode and the bottom electrode;
an insulative hydrogen barrier layer encapsulating on at least a sidewall of the individual ones of the plurality of memory devices;
a plate electrode coupled between the plurality of memory devices and the electrode structure, wherein the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices; and
a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices, and
wherein the individual ones of the plurality of via electrodes comprise:
a second conductive hydrogen barrier layer comprising a lateral portion and substantially vertical portions connected to two ends of the lateral portion; and
a second conductive fill material on the lateral portion and between the substantially vertical portions.